| contributor | Rechnerarchitektur (IFI) |
| creator | Irion, Alexander |
| Kiefer, Gundolf | |
| Vranken, Harald | |
| Wunderlich, Hans-Joachim | |
| date | 2001-03 |
| description | A divide-and-conquer approach using circuit partitioning is presented, which can be used to accelerate logic BIST synthesis procedures. Many BIST synthesis algorithms contain steps with a time complexity which increases more than linearly with the circuit size. By extracting sub-circuits which are almost constant in size, BIST synthesis for very large designs may be possible within linear time. The partitioning approach does not require any physical modifications of the circuit under test. Experiments show that significant performance improvements can be obtained at the cost of a longer test application time or a slight increase in silicon area for the BIST hardware. |
| identifier | http://www.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2001-78&engl=1 |
| ISBN: ISBN: 0-7695-0993-2 | |
| ISBN: ISSN: 1530- 159 1 | |
| ISBN: DOI: 10.1109/DATE.2001.915005 | |
| language | eng |
| publisher | Institute of Electrical and Electronics Engineers |
| source | In: Proceedings of the 4th Conference on Design, Automation and Test in Europe (DATE), Munich, Germany, March 12-16, 2001, pp. 86-91 |
| subject | Reliability, Testing, and Fault-Tolerance (CR B.8.1) |
| circuit partitionig | |
| deterministic BIST | |
| divide-and-conquer | |
| title | Circuit Partitioning for Efficient Logic BIST Synthesis |
| type | Text |
| Article in Proceedings |